In modern integrated circuits, semiconductor devices are formed on semiconductor substrates, and are connected through metallization layers. The metallization layers are interconnected to the semiconductor devices through contact plugs. Also, external pads are connected to the semiconductor devices through the contact plugs.
FIG. 1 illustrates conventional plugs for connecting the semiconductor devices to the metallization layers. Transistor 4, which symbolizes the semiconductor devices, is formed on semiconductor substrate 2. Inter-layer dielectric (ILD) 10 is formed on the semiconductor devices. Contact plugs 6 are formed in ILD 10 to connect source and drain regions 14 and gate 16 of transistor 4 to metal lines 7 in metallization layer 8. Typically, the formation of contact plugs 6 includes forming openings in ILD 10, and then filling the openings with tungsten plugs. A single damascene is then performed to form metallization layer 8.
With the increasing down-scaling of integrated circuits, the conventional contact plugs 6 experience shortcomings. While the horizontal dimensions, such as the width W of contact plugs 6, are continuously shrinking, the thickness T of ILD 10 is not reduced accordingly to the same scale as width W of contact plugs 6. Accordingly, the aspect ratio of contact plugs 6 continuously increases. This lack of proper scaling incurs several problems. For example, the top width W of contact plugs 6 is typically greater than the bottom width W′. Therefore, top corners of contact plugs 6 may be shortened, partially due to optical proximity effects and the inaccurate control of the etching processes. High aspect ratio also results in difficulties in the control of the bottom profile of contact openings, which in turn results in unexpected circuit degradation, and even device failure.
Accordingly, what is needed in the art is a new contact structure and formation methods for solving the above-discussed problems.